tiny ML Summit 2021 tiny Talks: Ultra-low Power and Scalable Compute-In-Memory AI Accelerator for…
tiny ML Summit 2021 https://www.tinyml.org/event/summit-2021
tinyTalks Hardware Optimization
Ultra-low Power and Scalable Compute-In-Memory AI Accelerator for Next Generation Edge Inference
Behdad YOUSSEFI, Founder and CEO, Areanna AI
Edge AI hardware accelerators are either deployed on Edge servers where sophisticated AI models run on a power budget between 1-10 Watts or on Edge devices where simple AI models run at milliwatts of power. But implementing more sophisticated AI models on Edge devices requires further development of ultra-low power architectures.
Research has shown that power consumption is dominated by data communication between memory and processor. To minimize data movement, the Compute-In-Memory (CIM) architecture has been explored by companies/academics. CIM is inherently a mixed signal architecture and hence requires data converters to interface between layers of network. However, data converters have proven to be the Achilles’ heel of this architecture as they take up to 98% of overall chip area and consume more than 85% of overall power consumption, defeating the whole purpose of CIM architecture. CIM also suffers from analog nonidealities which can degrade AI performance. Furthermore, the extra processing steps needed to fabricate the memory array in CIM limits the scalability of this architecture.
Areanna’s architecture addresses these issues using our proprietary Compute-and-Quantize-In-Memory (CQIM) architecture where SRAM bit-cells are repurposed to construct data converters, improving power/area efficiency by over an order of magnitude. Using logic gates as its building blocks, CQIM is inherently a digital architecture and scales well with the latest process nodes. High power efficiency and scalability of this architecture brings deployment of sophisticated real-time AI models with mW power budget within reach. A CQIM prototype is implemented and taped out in standard CMOS process.
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