tinyML Asia 2022 Weier Wan: Software Driven TinyML Hardware Co-Design
Software Driven TinyML Hardware Co-Design
Weier WAN, Head of Software-Hardware Co-design, Aizip
Software-hardware co-design is at the heart to enable efficient TinyML system. Over the past few years, the TinyML community has made tremendous progress: TinyML software developers have invented techniques to make AI models smaller, consume less memory, and requires less computation; TinyML hardware developers have designed accelerators chips that significantly lower inference latency and power consumption on TinyML benchmarks (e.g. MLPerf).
To realize further leap in efficiency, TinyML software and hardware should be more closely co-optimized from end-to-end. Accelerator hardware should be designed not just for models and metrics in public benchmarks, but also for robust models used in production and requirements from real-world tasks. Similarly, models and software should be optimized not just for the number of parameters and memory size, but also for full-system-level efficiency and cost.
Aizip is enabling the future of software-hardware co-design by offering accelerator co-design services to IC companies. The service leverages Aizip’s rich family of production quality TinyML models spanning vision, audio and time series applications. Aizip further co-designs accelerator hardware with its IC partners to most efficiently support these models, thereby combining the best of both worlds.
To reach the next-level efficiency, Aizip’s co-design service focuses on the processing-in-memory (PIM) AI accelerators. PIM accelerators significantly reduce AI inference power consumption by eliminating power-hungry data movements in conventional AI hardware. Aizip’s full-stack PIM co-design services includes silicon-verified PIM IPs, chip architecture design, PIM-optimized neural networks – PIMNets, and PIM-aware training frameworks. This full stack co-design ensures PIM products to deliver superior system-level energy-efficiency, while not compromising accuracy or robustness compared to digital processors.
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