tinyML Summit 2022: Programmable In-Memory Computing (IMC) Accelerator with 100 SRAM IMC Macros

tinyML Summit 2022
tinyML Hardware Session
Programmable In-Memory Computing (IMC) Accelerator with 100 SRAM IMC Macros
Jae-Sun SEO, Associate Professor, ASU

Artificial intelligence and deep neural networks (DNNs) have been successful across many practical applications, but state-of-the-art algorithms require a large amount of computation and memory. To resolve the computation and memory access bottleneck in conventional hardware accelerators, in-memory computing (IMC) has emerged as a promising technique. While many single-macro-level IMC prototypes have been demonstrated, integration and programmability challenges remain for system-level IMC accelerators. To that end, we present a programmable IMC accelerator (PIMCA) integrating 108 capacitive coupling based IMC SRAM macros of a total size of 3.4 Mb, together with 1.5 Mb off-the-self activation memory, demonstrating a large-scale SRAM-based IMC system hardware. We will discuss circuit techniques and architecture design employed for the PIMCA chip, including a custom ISA featuring IMC and SIMD functional units with special hardware loop control, supporting a range of DNN layer types with up to 4X smaller program size. The 28nm prototype chip achieves high system-level peak/average energy-efficiency of 437/289 TOPS/W.

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