RISC-V: How much is open source? Featuring the new ESP32-C3



When I got these new RISC-V ESP32 boards in my mail, I asked myself: Is this new technology revolutionary as written everywhere? What are the advantages for a typical Maker? Time for a closer look. But pay attention: It will be a rough ride and not for the fainthearted because we will talk about “stacks,” “IP,” “ecosystems,” and a lot about standardization.
If you hang on till the end, you should have enough knowledge to impress your boss. But maybe you will not be happy.
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Links:
Jeroen’s Video: https://youtu.be/X39nnPWmkvA

00:00 Intro
01:08 Content
01:42 What is RISC-V? / RISC / CISC
03:59 RISC / CISC History
04:57 The Technology Stack
06:39 Standardization and Flexibility
08:53 Most important Learning
09:33 ISA (Chip Architecture)
10:37 Corporate Strategies (why is ARM so successful?)
14:03 RTL, FPGAs, Verification
15:05 The Ecosystem
15:30 Who needs RISC-V?
16:16 Linux as an Example for Open Source development
16:44 Other Open Source Chips and why RISC-V’s timing is right
17:10 The Absent
17:33 The Proof (Nvidia bought ARM)
18:51 What is Open Source?
19:46 How to order our custom chip?
20:21 The ESP32-C3
22:10 There is Hope (SpriteTM and Hackaday)
22:41 The Future of RISC-V
23:37 Where to use the ESP32-C3?
24:04 Conclusions

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30 thoughts on “RISC-V: How much is open source? Featuring the new ESP32-C3

  • March 10, 2021 at 11:37 pm
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    ARM first was british (and is still for now) and used in Acorn british microcomputer Acorn Archimed.
    It has been used in lot of computer/hardware before apple, and now half of higher part of top ten supercomputers are based on RISC architecture (first ARM by Fujitsu, Japan, then Power by IBM, USA, then Shunway, from China, the last one is the first to start new generation RISC in super-computers. European community is currently working on a continental made processor for supercalculator, mixing RISC ARM and RISC-V technologies. The first test supercomputer implementation is in Barcelona, and already powerfull.
    There are lot of RISC-V interesting cheap and powerfull boards, like Sipeed implementations, still in microcontroller market. But high frequency RISC-V chip come fastly, with Starfive processor runing at 3.5Ghz, you don't speak about V (ector processor) extension in RISC-V, this is a comeback of a very really powerfull architecture for massive computation, and will be a very interesting point in this standard, that lot of enterprises want.

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  • March 10, 2021 at 11:37 pm
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    In a led driver that I've bought recently there was a chip BL602 from Bouffalo labs. It's also a Risc V chip and probably suits well for large volumes. So, maybe is the new path for some embedded devices. Two months ago I wanted to investigate. But on the other hand also Expressif is about to launch the ESP32-S3 that seems impressive (at least on paper) and also comes with a Risc V low power processor. I think I'll wait for it.

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  • March 10, 2021 at 11:37 pm
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    Crucially, the main aspect of RISC-V which is not open-source, is any individual implementation. One can not independently verify that the chip you have in your hand precisely matches the behavior of the open-source RTL that defines any particular RISC-V. In fact, the implementation most assuredly will differ. At the very least, manufacturing test structures that provide deep observability into the state of the uProc will have been added, frequently along with on-chip instrumentation. What is not open-source between RTL and silicon that should be for any device is: post-synthesis gate-level net-list byproduct of the place-and-route step along with the technology libraries, the LEF and DEF that describe the layout and, finally the GDS-II for the device. But, RISC-V providers will not release any of these design descriptions.

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  • March 10, 2021 at 11:37 pm
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    One of the big omissions is the VLIW processors, like the Itanium that Intel and HP cooperated on (It even had a Windows XP release)

    Windows NT supported several architectures….

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  • March 10, 2021 at 11:37 pm
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    Would be interesting to see some ADC tests on the new ESP32-C3. Espressif do not seem to have a good track record for producing decent ADCs compared to their competitors.

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  • March 10, 2021 at 11:37 pm
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    Can you explain why MIPS was not successful? Microchip advertised this some years ago as the future of their dsPICs

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  • March 10, 2021 at 11:37 pm
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    Thank you Andreas; excellent information and extremely clear.

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  • March 10, 2021 at 11:37 pm
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    Ok… Nice video. I appreciated the details about RISC-V. You said at the start that you simplify things but they can mislead.
    1. The early broad programming APIs were UNIX system calls and in the 8080 based operating system CPM. Microsoft's DOS was based on this but took standardisation many steps further with the idea of device drivers and DOS interrupts. 16 bit windows built in DOS.
    2. Windows NT, later becoming the modern Windows, has long supported compilation to non-x86 ISAs. Originally, PowerPC, MIPS, Alpha, as well as Intel.
    3. Originally Intel had partnered with AMD to produce some CPUs, like 40MHz 386 and 486 as well as some 286, from memory. That's how AMD became an x86 licensee. I had a 386 that had both AMD and Intel's name on it.

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  • March 10, 2021 at 11:37 pm
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    Excellent! I really appreciate the historical background (even if very subjective and abbreviated) and the effort you put into explaining the economic context.

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  • March 10, 2021 at 11:37 pm
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    A few minor issues that I would like to correct:
    RISC architectures are generally slower than a well developed CISC one within the scope of applications that it were developed for. Since the CISC architecture can leverage more advanced functions to do more work without needing to cycle through any control logic between operations within the instruction. While a RISC architecture will need to implement the same instruction with a set of simpler instructions, where each of these instructions will need to be processed by our control logic. This decreases the performance of the RISC architecture, and usually also the power efficiency as well. Even with instruction compression (aka microcode) this problem still remains. (and yes, x86 does contain microcode as well, but then it is typically building further on top of what it already has. It does also do some simplifications of some instructions, but x86 is CISC. But x86 isn't a perfect CISC architecture, nor the only CISC architecture.)

    And your example of compiler complexity in regards to CISC and RISC, it is typically the opposite to what you described.
    Compiling on CISC tends to require more effort than a RISC architecture. Since we can't measure the intensity of the work of converting our code to instructions by how many instructions were required in the end product. It would be like comparing the complexity of a given code based on how many lines including comments it consists out of.

    Having RISC as a standardized ISA is also a bit bogus. Since different architectures can take fairly drastically different approaches to similar problems, for larger system related reasons, making it infeasible for them to share a common ISA. Ie, the future of RISC-V isn't going to create a standardized ISA in the market. And to be fair, even GNU/Linux is very fragmented in its support due to its various distributions that makes running software on it a living hell at times. ARM already is fairly fractured in a similar fashion, where one ARM chip doesn't run/support stuff natively, even if stuff is compiled for ARM. RISC-V is likely to end up in a similar situation in fairly short order. Making the standard more strict will only limit RISC-V's ability to be applicable for more varying approaches to architectures.

    In the end.
    The main advantages for RISC-V is that it can be used as a lower cost alternative to ARM in some sections. Where device makers can adapt the core to their needs without having to undergo the development of the whole thing themselves. In higher performance markets, it to a degree will have issues competing, since the RISC-V ISA is fairly limited in what architectures it can implement.

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  • March 10, 2021 at 11:37 pm
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    Hello again from Tokyo Andreas! I felt the same way so we became RISC-V members.

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  • March 10, 2021 at 11:37 pm
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    Waiting for them to be released, since I consider them for a new product my company is considering.

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  • March 10, 2021 at 11:37 pm
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    Actually the possibility to create very simple processors (even Arm as you showed carry along a lot of legacy instructions) opens up the possibility to create quite/very fast (clock speed) processors with a quite low power usage per performance.

    Reply

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